HD64F2145 Datasheet, PDF (465/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

FS=1 and FSX=1
S
DATA
1
8
1
DATA
n
m
P
1 _{Transfer bit count}
(n = 1 to 8)
Transfer frame count
(m = from 1)
Figure 16.5 I²C Bus Data Format (Serial Format)
SDA
SCL
1–7
8
9
1–7
8
9
1–7
8
9
S
SLA
R/
A
DATA
A
DATA
A/
P
Figure 16.6 I²C Bus Timing
Table 16.6 I²C Bus Data Format Symbols
Legend
S
SLA
R/:
A
DATA
P
Start condition. The master device drives SDA from high to low while SCL is high
Slave address. The master device selects the slave device.
Indicates the direction of data transfer: from the slave device to the master device
when R/: is 1, or from the master device to the slave device when R/: is 0
Acknowledge. The receiving device drives SDA low to acknowledge a transfer. (The
slave device returns acknowledge in master transmit mode, and the master device
returns acknowledge in master receive mode.)
Transferred data. The bit length of transferred data is set with the BC2 to BC0 bits in
ICMR. The MSB first or LSB first is switched with the MLS bit in ICMR.
Stop condition. The master device drives SDA from low to high while SCL is high
Rev. 2.0, 08/02, page 425 of 788