HD64F2145 Datasheet, PDF (128/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

5.3.1 Interrupt Control Registers A to C (ICRA to ICRC)
The ICR registers set interrupt control levels for interrupts other than NMI and address breaks.
The correspondence between interrupt sources and ICRA to ICRC settings is shown in table 5.2.
Bit Bit Name Initial Value R/W
7
ICRn7
All 0
R/W
to
to
0
IRCn0
n: A to C
Description
Interrupt Control Level
0: Corresponding interrupt source is interrupt
control level 0 (no priority)
1: Corresponding interrupt source is interrupt
control level 1 (priority)
Table 5.2 Correspondence between Interrupt Source and ICR
Register
Bit Bit Name
ICRA
ICRB
ICRC
7
ICRn7
IRQ0
A/D converter
SCI_0
6
ICRn6
IRQ1
FRT
SCI_1
5
ICRn5
IRQ2, IRQ3
—
SCI_2
4
ICRn4
IRQ4, IRQ5
—
IIC_0
3
ICRn3
IRQ6, IRQ7
TMR_0
IIC_1
2
ICRn2
DTC
TMR_1
—
1
ICRn1
WDT_0
TMR_X , TMR_Y
LPC*
0
ICRn0
WDT_1
XBS,
—
Keyboard buffer controller
n: A to C
: Reserved. The write value should always be 0.
Note:* On products not including LPC, this bit is reserved. The write value should always be 0.
Rev. 2.0, 08/02, page 88 of 788