HD64F2145 Datasheet, PDF (174/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

6.8 Bus Arbitration
The bus controller has a bus arbiter that arbitrates bus master operations. There are two bus
masters – the CPU and DTC – that perform read/write operations when they have possession of
the bus.
6.8.1 Priority of Bus Masters
Each bus master requests the bus by means of a bus request signal. The bus arbiter detects the bus
masters' bus request signals, and if a bus request occurs, it sends a bus request acknowledge signal
to the bus master making the request at the designated timing. If there are bus requests from more
than one bus master, the bus request acknowledge signal is sent to the one with the highest
priority. When a bus master receives the bus request acknowledge signal, it takes possession of the
bus until that signal is canceled. The order of priority of the bus masters is as follows:
(High) DTC > CPU (Low)
6.8.2 Bus Transfer Timing
When a bus request is received from a bus master with a higher priority than that of the bus master
that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. Each bus master can relinquish the bus at the timings given below.
CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC,
the bus arbiter transfers the bus to the DTC.
• DTC bus transfer timing
 The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in
discrete operations, as in the case of a longword-size access, the bus is not transferred
between the component operations. For details, refer to the H8S/2600 Series, H8S/2000
Series Programming Manual.
 If the CPU is in sleep mode, the bus is transferred immediately.
DTC: The DTC has the highest bus master priority. The DTC sends the bus arbiter a request for
the bus when an activation request is generated. The DTC does not release the bus until it
completes its operation.
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