HD64F2145 Datasheet, PDF (334/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

12.9.4 Conflict between Compare-Matches A and B
If compare-matches A and B occur at the same time, the 8-bit timer operates in accordance with
the priorities for the output states set for compare-match A and compare-match B, as shown in
table 12.5.
Table 12.5 Timer Output Priorities
Output Setting
Toggle output
1 output
0 output
No change
Priority
High
Low
12.9.5 Switching of Internal Clocks and TCNT Operation
TCNT may increment erroneously when the internal clock is switched over. Table 12.6 shows the
relationship between the timing at which the internal clock is switched (by writing to the CKS1
and CKS0 bits) and the TCNT operation.
When the TCNT clock is generated from an internal clock, the falling edge of the internal clock
pulse is detected. If clock switching causes a change from high to low level, as shown in no. 3 in
table 12.6, a TCNT clock pulse is generated on the assumption that the switchover is a falling
edge, and TCNT is incremented.
Erroneous incrementation can also happen when switching between internal and external clocks.
Rev. 2.0, 08/02, page 294 of 788