HD64F2145 Datasheet, PDF (295/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

11.5.3 FRC Clear Timing
FRC can be cleared when compare-match A occurs. Figure 11.6 shows the timing of this
operation.
ø
Compare-match
A signal
FRC
N
H'0000
Figure 11.6 Clearing of FRC by Compare-Match A Signal
11.5.4 Input Capture Input Timing
The rising or falling edge can be selected for the input capture input timing by the IEDGA to
IEDGD bits in TCR. Figure 11.7 shows the usual input capture timing when the rising edge is
selected.
ø
Input capture
input pin
Input capture signal
Figure 11.7 Input Capture Input Signal Timing (Usual Case)
Rev. 2.0, 08/02, page 255 of 788