HD64F2145 Datasheet, PDF (818/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Item
Page
21.3.2 A/D Control/Status 563
Register (ADCSR)
563
564
21.4.3 Input Sampling and 568
A/D Conversion Time
Figure 21.3 A/D
Conversion Timing
Revisions (See Manual for Details)
Description of bit 5 added.
Setting this bit to 1 starts A/D conversion. Clearing this bit to 0
stops A/D conversion. In single mode, this bit is cleared to 0
automatically when conversion on the specified channel ends.
Bit 4
(Error)
Selects the A/D conversion operating mode. The setting of this
bit must be made while conversion is halted.
(Correction)
Selects the A/D conversion operating mode. The setting of this
bit must be made when conversion is halted (ADST = 0).
Bit 3
(Error)
Sets A/D conversion time.
(Correction)
Sets A/D conversion time. The input channel setting must be
made when conversion is halted (ADST = 0).
Bits 2 to 0
(Error)
Select analog input channels. The input channel setting must
be made while conversion is halted.
(Correction)
Select analog input channels. The input channel setting must
be made when conversion is halted (ADST = 0).
(Error)
(Correction)
(1)
(1)
Write signal
Write signal
21.7.6 Module Stop Mode 574
Setting
Section 22 RAM
575
Section 23 ROM
577
23.1 Features
• Size
Added.
List added.
List of ROM capacitance added.
Rev. 2.0, 08/02, page 778 of 788