HD64F2145 Datasheet, PDF (186/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 7.3 Register Functions in Repeat Mode
Name
DTC source address register
DTC destination address register
DTC transfer count register AH
DTC transfer count register AL
DTC transfer count register B
Abbreviation
SAR
DAR
CRAH
CRAL
CRB
Function
Transfer source address
Transfer destination address
Holds number of transfers
Transfer Count
Not used
SAR
or
DAR
Repeat area
Transfer
DAR
or
SAR
Figure 7.6 Memory Mapping in Repeat Mode
7.5.3 Block Transfer Mode
In block transfer mode, one activation source transfers one block of data. Either the transfer source
or the transfer destination is designated as a block area. Table 7.4 lists the register functions in
block transfer mode. The block size can be between 1 and 256. When the transfer of one block
ends, the initial state of the block size counter and the address register that is specified as the block
area is restored. The other address register is then incremented, decremented, or left fixed
according to the register information. From 1 to 65,536 transfers can be specified. Once the
specified number of transfers have been completed, a CPU interrupt is requested.
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