HD64F2145 Datasheet, PDF (179/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

In repeat mode or block transfer mode, the CRA is divided into two parts; the upper 8 bits
(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL
functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is
transferred, and the contents of CRAH are sent when the count reaches H'00.
7.2.6 DTC Transfer Count Register B (CRB)
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.
7.2.7 DTC Enable Registers (DTCER)
DTCER specifies DTC activation interrupt sources. DTCER is comprised of five registers:
DTCERA to DTCERE. The correspondence between interrupt sources and DTCE bits is shown in
table 7.1. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR.
Multiple DTC activation sources can be set at one time (only at the initial setting) by masking all
interrupts and writing data after executing a dummy read on the relevant register.
Bit Bit Name
7 DTCE7
6 DTCE6
5 DTCE5
4 DTCE4
3 DTCE3
2 DTCE2
1 DTCE1
0 DTCE0
Initial Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
DTC Activation Enable
Setting this bit to 1 specifies a relevant interrupt source
as a DTC activation source.
[Clearing conditions]
• When data transfer has ended with the DISEL bit in
MRB set to 1.
• When the specified number of transfers have ended.
[Holding condition]
• When the DISEL bit is 0 and the specified number of
transfers have not been completed.
Rev. 2.0, 08/02, page 139 of 788