HD64F2145 Datasheet, PDF (766/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Condition Condition Condition
A
B
C
Item
Sym- ^{10 MHz 16 MHz 20 MHz}
Test
bol Min Max Min Max Min Max Unit Conditions
TMR Timer clock Single edge t_TMCWH 1.5 — 1.5 — 1.5 — t_cyc Figure
pulse width _{Both edges tTMCWL 2.5 — 2.5 — 2.5 —}
28.20
PWM, Pulse output delay time
t
PWOD
—
100 — 50 — 50 ns Figure
PWMX
28.22
SCI Input clock Asynchronous t_Scyc
4
—4
—4
— t_cyc Figure
cycle
Synchronous
6 —6 — 6 —
28.23
Input clock pulse width t
SCKW
Input clock rise time
t
SCKr
Input clock fall time
t_SCKf
Transmit data delay time t_TXD
(clocked synchronous)
0.4 0.6 0.4 0.6 0.4 0.6 t
cscyc
— 1.5 — 1.5 — 1.5 t
cyc
— 1.5 — 1.5 — 1.5
— 100 — 50 — 50 ns Figure
28.24
Receive data setup time
t
RXS
(clocked synchronous)
100 — 50 — 50 —
Receive data hold time t
RXH
(clocked synchronous)
100 — 50 — 50 —
A/D Trigger input setup time
converter
t
TRGS
50 — 30 — 30
WDT 5(62 output delay time
t
RESD
—
200 — 120 —
5(62 output pulse width
t
RESOW
132 — 132 —
132
Note:* Only peripheral modules that can be used in subclock operation
— ns
100 ns
—t
cyc
Figure
28.25
Figure
28.26
Rev. 2.0, 08/02, page 726 of 788