HD64F2145 Datasheet, PDF (370/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

• TCSR_1
Bit Bit Name Initial Value R/W Description
7
OVF
0
R/(W)*¹ Overflow Flag
Indicates that TCNT has overflowed (changes from H’FF
to H’00).
[Setting condition]
When TCNT overflows (changes from H’FF to H’00)
However, when internal reset request generation is
selected in watchdog timer mode, OVF is cleared
automatically by the internal reset.
[Clearing conditions]
When TCSR is read when OVF = 1*², then 0 is written to
OVF
When 0 is written to TME
6
WT/,7 0
R/W Timer Mode Select
Selects whether the WDT is used as a watchdog timer or
interval timer.
0: Interval timer mode
1: Watchdog timer mode
5
TME
0
R/W Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and is
initialized to H'00.
Rev. 2.0, 08/02, page 330 of 788