HD64F2145 Datasheet, PDF (277/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

1 conversion cycle
t_f1
t_f2
t_f255
t_f256
t_H1
t_H2
t_H3
t_f1 = t_f2 = t_f3 = ··· = t_f255 = t_f256 = T 64
t_H1 + t_H2 + t_H3 + ··· + t_H255 + t_H256 = T_H
t_H255
a. CFS = 0 [base cycle = resolution (T) 64]
1 conversion cycle
t_f1
t_f2
t_f63
t_H256
t_f64
t_H1
t_H2
t_H3
t_f1 = t_f2 = t_f3 = ··· = t_f63 = t_f64 = T 256
t_H1 + t_H2 + t_H3 + ··· + t_H63 + t_H64 = T_H
t_H63
t_H64
b. CFS = 1 [base cycle = resolution (T) 256]
Figure 10.4 Output Waveform (OS = 1, DADR corresponds to T_H)
An example of setting CFS to 1 (basic cycle = resolution (T) × 256) and OS to 1 (PWMX inverted
output) is shown as an additional pulse. When CFS is set to 1, the duty ratio of the basic pulse is
determined by the upper eight bits (DA13 to DA6) in DADR, and the position of the additional
pulse is determined by the following six bits (DA5 to DA0) as shown in figure 10.5.
Table 10.4 shows the position of the additional pulse.
DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS
Basic pulse duty ratio
Additional pulse position
1
1
Figure 10.5 D/A Data Register Configuration when CFS = 1
Here, the case of DADR = H’0207 (B’0000 0010 0000 0111) is considered. Figure 10.6 shows an
output waveform. Because CFS = 1 and the value of upper eight bits is B’0000 0010, the duty
ratio of the basic pulse is 2/256 × (T) of high width.
Since the value of the following six bits is B’0000 01, the additional pulse is output at the position
of basic pulse No. 63 as shown in table 10.4. Only 1/256 × (T) of the additional pulse is added to
the basic pulse.
Rev. 2.0, 08/02, page 237 of 788