HD64F2145 Datasheet, PDF (132/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

5.3.6 IRQ Status Register (ISR)
The ISR register is a flag register that indicates the status of IRQ7 to IRQ0 interrupt requests.
Bit Bit Name Initial Value R/W
Description
7
IRQ7F
0
R/(W)*² [Setting condition]
6
IRQ6F
0
5
IRQ5F
0
4
IRQ4F
0
3
IRQ3F
0
2
IRQ2F
0
1
IRQ1F
0
0
IRQ0F
0
R/(W)*²
R/(W)* ²
R/(W)* ²
R/(W)* ²
R/(W)* ²
R/(W)* ²
R/(W)* ²
When the interrupt source selected by the ISCR
registers occurs
[Clearing conditions]
• When reading IRQnF flag when IRQnF = 1,
then writing 0 to IRQnF flag
• When interrupt exception handling is
executed when low-level detection is set
and ,54Q input is high
(n = 7 to 0)*¹
• When IRQn interrupt exception handling is
executed when falling-edge, rising-edge, or
both-edge detection is set*¹
Notes: 1. When a product, in which a DTC is incorporated, is used, the corresponding flag bit is
not automatically cleared even when exception handing is executed. For details, refer to
section 5.8.4, Setting on a Product Incorporating DTC.
2. Only 0 can be written, for flag clearing.
5.3.7
Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR)
Wake-Up Event Interrupt Mask Register (WUEMRB)
The KMIMRA, KMIMR, and WUEMRB registers enable or disable key-sensing interrupt inputs
(.,148 to .,13), and wake-up event interrupt inputs (:8(: to :8(3).
• KMIMRA
Bit Bit Name Initial Value R/W
7
KMIMR15 1
R/W
6
KMIMR14 1
R/W
5
KMIMR13 1
R/W
4
KMIMR12 1
R/W
3
KMIMR11 1
R/W
2
KMIMR10 1
R/W
1
KMIMR9 1
R/W
0
KMIMR8 1
R/W
Description
Keyboard Matrix Interrupt Mask 15 to 8
These bits enable or disable a key-sensing
input interrupt request (KIN15 to KIN8).
0: Enables a key-sensing input interrupt request
1: Disables a key-sensing input interrupt
request
Rev. 2.0, 08/02, page 92 of 788