HD64F2145 Datasheet, PDF (662/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

• MSTPCRL
Bit Bit Name Initial Value R/W Corresponding Module
7 MSTP7 1
R/W Serial communication interface_0 (SCI_0)
6 MSTP6 1
R/W Serial communication interface_1 (SCI_1)
5 MSTP5 1
R/W Serial communication interface_2 (SCI_2)
4 MSTP4 1
R/W I²C bus interface_0 (IIC_0)
3 MSTP3 1
R/W I²C bus interface_1 (IIC_1)
2 MSTP2 1
R/W Host interface (XBS), keyboard buffer controller, keyboard
matrix interrupt mask register (KMIMR), keyboard matrix
interrupt mask register A (KMIMRA), port 6 pull-up MOS
control register (KMPCR)
1 MSTP1 1*
R/W 
0 MSTP0 1
R/W Host interface (LPC), wake-up event interrupt mask register
B (WUEMRB)
Note:* This bit can be read from or written to, however, operation is not affected.
26.2 Mode Transitions and LSI States
Figure 26.1 shows the enabled mode transition diagram. The mode transition from program
execution state to program halt state is performed by the SLEEP instruction. The mode transition
from program halt state to program execution state is performed by an interrupt. The 67%< input
causes a mode transition from any state to hardware standby mode. The 5(6 input causes a mode
transition from a state other than hardware standby mode to the reset state. Table 26.2 shows the
LSI internal states in each operating mode.
Rev. 2.0, 08/02, page 622 of 788