HD64F2145 Datasheet, PDF (813/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Item
14.4.1 Watchdog Timer
Mode
Figure 14.2 Watchdog
Timer Mode (RST/10, =
1) Operation
Page
333
Revisions (See Manual for Details)
Corrected.
TCNT value
H'FF
Overflow
H'00
WT/ = 1Write H'00 to
TME = 1 TCNT
signal
Time
OVF = 1* WT/ = 1Write H'00 to
TME = 1 TCNT
and internal reset signals generated
Internal reset signal
132 system clocks
WT/ : Timer mode select bit
518 system clocks
TME : Timer enable bit
OVF : Overflow flag
Note * After the OVF bit becomes 1, it is cleared to 0 by an internal reset.
The XRST bit is also cleared to 0.
14.6 Usage Notes
338
14.6.7 OVF Flag Clear
Condition
Section 15 Serial
339
Communication Interface
(SCI and IrDA)
15.1 Features
340
15.3.2 Receive Data
342
Register (RDR)
15.3.3 Transmit Data
342
Register (TDR)
16.3.5 I²C Bus Control 406
Register (ICCR)
Deleted.
(Error)
• Module stop mode availability
(Correction)
Deleted.
(Error)
A block diagram of SCI_1 is shown in figure 15.1.
(Correction)
A block diagram of the SCI is shown in figure 15.1.
Description added.
After confirming that the RDRF bit in SSR is set to 1, read
RDR for only once. RDR cannot be written to by the CPU.
RDR is initialized to H'00.
Description added.
Although TDR can be read from or written to by the CPU at all
times, to achieve reliable serial transmission, write transmit
data to TDR for only once after confirming that the TDRE bit in
SSR is set to 1. TDR is initialized to H'FF.
(Error)
assuming that the start condition has been issued.
(Correction)
assuming that the stop condition has been issued.
Rev. 2.0, 08/02, page 773 of 788