HD64F2145 Datasheet, PDF (496/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

6. The I²C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
and 300 ns. The I²C bus interface SCL and SDA output timing is prescribed by t_cyc, as shown in
table 16.9. However, because of the rise and fall times, the I²C bus interface specifications may
not be satisfied at the maximum transfer rate. Table 16.11 shows output timing calculations for
different operating frequencies, including the worst-case influence of rise and fall times.
t_BUFO fails to meet the I²C bus interface specifications at any frequency. The solution is either (a)
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I²C bus.
t_SCLLO in high-speed mode and t_STASO in standard mode fail to satisfy the I²C bus interface
specifications for worst-case calculations of t_Sr/t_Sf. Possible solutions that should be investigated
include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load,
(b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input
timing permits this output timing for use as slave devices connected to the I²C bus.
Rev. 2.0, 08/02, page 456 of 788