HD64F2145 Datasheet, PDF (473/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Master receive mode
Set TRS = 0 in ICCR
Set ACKB = 0 in ICSR
Set HNDS = 0 in ICXR
Clear IRIC flag in ICCR
Set WAIT = 1 in ICMR
Read ICDR
Read IRIC flag in ICCR
No
IRIC = 1?
Yes
No
IRTR = 1?
Yes
Last receive? ^Yes
No
Read ICDR
Clear IRIC flag in ICCR
Set ACKB = 1 in ICSR
Wait for one clock pulse
Set TRS = 1 in ICCR
Read ICDR
Clear IRIC flag in ICCR
[1] Select receive mode.
[2] Start receiving. The first read
is a dummy read.
[3] Wait for a receive wait
(Set IRIC at the fall of the 8th clock) or,
Wait for 1 byte to be received
(Set IRIC at the rise of the 9th clock)
[4] Determine end of reception
[5] Read the receive data.
[6] Clear IRIC flag.
(to end the wait insertion)
[7] Set acknowledge data for the last reception.
[8] Wait for TRS setting
[9] Set TRS for stop condition issuance
[10] Read the receive data.
[11] Clear IRIC flag. (to end the wait insertion)
Read IRIC flag in ICCR
No
IRIC=1?
Yes
IRTR=1?
Yes
No
Clear IRIC flag in ICCR
[12] Wait for a receive wait
(Set IRIC at the fall of the 8th clock) or,
Wait for 1 byte to be received
(Set IRIC at the rise of the 9th clock)
[13] Determine end of reception
[14] Clear IRIC.
(to end the wait insertion)
Set WAIT = 0 in ICMR
Clear IRIC flag in ICCR
Read ICDR
Set BBSY= 0 and SCP= 0
in ICCR
End
[15] Clear wait mode.
Clear IRIC flag.
( IRIC flag should be cleared to 0
after setting WAIT = 0.)
[16] Read the last receive data.
[17] Generate stop condition
Figure 16.14 Sample Flowchart for Operations in Master Receive Mode
(receiving multiple bytes) (WAIT = 1)
Rev. 2.0, 08/02, page 433 of 788