HD64F2145 Datasheet, PDF (18/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

15.3 Register Descriptions ........................................................................................................341
15.3.1 Receive Shift Register (RSR)...............................................................................342
15.3.2 Receive Data Register (RDR) ..............................................................................342
15.3.3 Transmit Data Register (TDR) .............................................................................342
15.3.4 Transmit Shift Register (TSR) .............................................................................342
15.3.5 Serial Mode Register (SMR)................................................................................343
15.3.6 Serial Control Register (SCR)..............................................................................345
15.3.7 Serial Status Register (SSR).................................................................................347
15.3.8 Serial Interface Mode Register (SCMR) ..............................................................349
15.3.9 Bit Rate Register (BRR).......................................................................................350
15.3.10 Keyboard Comparator Control Register (KBCOMP) ..........................................356
15.4 Operation in Asynchronous Mode.....................................................................................357
15.4.1 Data Transfer Format ...........................................................................................357
15.4.2 Receive Data Sampling Timing and Reception Margin
in Asynchronous Mode ........................................................................................359
15.4.3 Clock ....................................................................................................................360
15.4.4 SCI Initialization (Asynchronous Mode) .............................................................361
15.4.5 Data Transmission (Asynchronous Mode)...........................................................362
15.4.6 Serial Data Reception (Asynchronous Mode) ......................................................364
15.5 Multiprocessor Communication Function.........................................................................368
15.5.1 Multiprocessor Serial Data Transmission ............................................................370
15.5.2 Multiprocessor Serial Data Reception..................................................................371
15.6 Operation in Clocked Synchronous Mode ........................................................................374
15.6.1 Clock ....................................................................................................................374
15.6.2 SCI Initialization (Clocked Synchronous Mode) .................................................375
15.6.3 Serial Data Transmission (Clocked Synchronous Mode).....................................376
15.6.4 Serial Data Reception (Clocked Synchronous Mode)..........................................378
15.6.5 Simultaneous Serial Data Transmission and Reception
(Clocked Synchronous Mode) ..............................................................................380
15.7 IrDA Operation .................................................................................................................382
15.8 Interrupt Sources ...............................................................................................................385
15.9 Usage Notes.......................................................................................................................386
15.9.1 Module Stop Mode Setting ..................................................................................386
15.9.2 Break Detection and Processing...........................................................................386
15.9.3 Mark State and Break Detection ..........................................................................386
15.9.4 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only) .....................................................................386
15.9.5 Relation between Writing to TDR and TDRE Flag .............................................386
15.9.6 Restrictions on Using DTC ..................................................................................387
15.9.7 SCI Operations during Mode Transitions.............................................................387
15.9.8 Notes on Switching from SCK Pins to Port Pins..................................................391
Rev. 2.0, 08/02, page xvi of xxxviii