HD64F2145 Datasheet, PDF (665/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Function
High-
Speed
Medium-
Speed Sleep
Module
Stop
Watch
Sub-
Active
Sub-
Sleep
Software Hardware
Standby Standby
Peripheral PWM
modules
PWMX
XBS,
Keyboard
buffer
controller
Function-
ing
Function- Function-
ing
ing
Function- Halted
ing/Halted (reset)
(reset)
Halted
(reset)
Halted
(reset)
Halted
(reset)
Halted
(reset)
D/A
A/D
RAM
Function- Function- Retained Function- Retained Retained Retained
ing (DTC) ing
ing
I/O
Function- Function- Retained Function- Function- Retained High
ing
ing
ing
ing
impedance
Note:* “Halted (retained)” means that internal register values are retained. The internal state is
“operation suspended.”
“Halted (reset)” means that internal register values and internal states are initialized.
In module stop mode, only modules for which a stop setting has been made are halted
(reset or retained).
26.3 Medium-Speed Mode
The CPU makes a transition to medium-speed mode as soon as the current bus cycle ends
according to the setting of the SCK2 to SCK0 bits in SBYCR. In medium-speed mode, the CPU
operates on the operating clock (ø/2, ø/4, ø/8, ø/16, or ø/32). On-chip peripheral modules other
than the bus masters always operate on the system clock (ø).
In medium-speed mode, a bus access is executed in the specified number of states with respect to
the bus master operating clock. For example, if ø/4 is selected as the operating clock, on-chip
memory is accessed in 4 states, and internal I/O registers in 8 states.
By clearing all of bits SCK2 to SCK0 to 0, a transition is made to high-speed mode at the end of
the current bus cycle.
If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, and the LSON
bit in LPWRCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by
an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the
SSBY bit set to 1, the LSON bit cleared to 0, and the PSS bit in TCSR (WDT_1) cleared to 0,
operation shifts to software standby mode. When software standby mode is cleared by an external
interrupt, medium-speed mode is restored.
When the 5(6 pin is set low and medium-speed mode is cancelled, operation shifts to the reset
state. The same applies in the case of a reset caused by overflow of the watchdog timer.
Rev. 2.0, 08/02, page 625 of 788