HD64F2145 Datasheet, PDF (733/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 28.9 Keyboard Buffer Controller Timing
Conditions: V_CC = 2.7 V to 3.6 V, V_CCB = 2.7 V to 5.5 V, V_SS = 0 V, ø = 2 MHz to maximum
operating frequency, T_a = –20 to +75°C
Item
Symbol
KCLK, KD output fall time
t
KBF
KCLK, KD input data hold time t_KBIH
KCLK, KD input data setup time t_KBIS
KCLK, KD output delay time
t_KBOD
KCLK, KD capacitive load
C_b
Ratings
Min
Typ
20 + 0.1Cb —
150
—
150
—
—
—
—
—
Max
250
—
—
450
400
Unit
ns
ns
ns
ns
pF
Test
Conditions Notes
Figure
28.28
Table 28.10 I²C Bus Timing
Conditions: V_CC = 2.7 V to 3.6 V, V_SS = 0 V, ø = 5 MHz to maximum operating frequency,
T_a = –20 to +75°C
Item
Ratings
Symbol Min Typ Max Unit
Test
Conditions Notes
SCL input cycle time
t_SCL
SCL input high pulse width
t_SCLH
SCL input low pulse width
t
SCLL
SCL, SDA input rise time
t
Sr
SCL, SDA input fall time
t
Sf
SCL, SDA input spike pulse
t_SP
elimination time
12
—
—
t_cyc
3
—
—
t_cyc
5
——t
cyc
—
—
7.5*
t
cyc
— — 300 ns
——1
t_cyc
Figure
28.29
SDA input bus free time
t
BUF
Start condition input hold time t
STAH
Retransmission start condition t
STAS
input setup time
5
——t
cyc
3
——t
cyc
3
——t
cyc
Stop condition input setup time t
STOS
3
——t
cyc
Data input setup time
t
SDAS
0.5 — — t
cyc
Data input hold time
t
SDAH
0
— — ns
SCL, SDA capacitive load
C_b
— — 400 pF
Note:* 17.5 t_cyc can be set according to the clock selected for use by the I²C module. For details,
see section 16.6, Usage Notes.
Rev. 2.0, 08/02, page 693 of 788