HD64F2145 Datasheet, PDF (371/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit Bit Name Initial Value R/W Description
4
PSS
0
R/W Prescaler Select
Selects the clock source to be input to TCNT.
0: Counts the divided cycle of ø–based prescaler (PSM)
1: Counts the divided cycle of øSUB–based prescaler
(PSS)
3
RST/10, 0
R/W Reset or NMI
Selects to request an internal reset or an NMI interrupt
when TCNT has overflowed.
0: An NMI interrupt is requested
1: An internal reset is requested
2
CKS2 0
R/W Clock Select 2 to 0
1
CKS1 0
0
CKS0 0
R/W Selects the clock source to be input to TCNT. The
R/W ^{overflow cycle for ø = 10 MHz and øSUB = 32.768 kHz is}
enclosed in parentheses.
When PSS = 0:
000: ø/2 (frequency: 51.2 µs)
001: ø/64 (frequency: 1.64 ms)
010: ø/128 (frequency: 3.28 ms)
011: ø/512 (frequency: 13.1 ms)
100: ø/2048 (frequency: 52.4 ms)
101: ø/8192 (frequency: 209.7 ms)
110: ø/32768 (frequency: 0.84 s)
111: ø/131072 (frequency: 3.36 s)
When PSS = 1:
000: øSUB/2 (cycle: 15.6 ms)
001: øSUB/4 (cycle: 31.3 ms)
010: øSUB/8 (cycle: 62.5 ms)
011: øSUB/16 (cycle: 125 ms)
100: øSUB/32 (cycle: 250 ms)
101: øSUB/64 (cycle: 500 ms)
110: øSUB/128 (cycle: 1 s)
111: ø/256 (cycle: 2 s)
Notes: 1. Only 0 can be written, to clear the flag.
2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at
least twice.
Rev. 2.0, 08/02, page 331 of 788