HD64F2145 Datasheet, PDF (524/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Figure 18.1 shows a block diagram of the XBS.
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HA0
Internal interrupt signals
IBF4 IBF3 IBF2 IBF1
Control logic
Host
interrupt
request
Fast
A20 gate
control
HIRQ1
HIRQ11
HIRQ12
HIRQ3
HIRQ4
GA20
HIFSD
Port 4, port 8, port B
HDB7 to HDB0
IDR_1
ODR_1
STR_1
IDR_2
ODR_2
STR_2
HICR
IDR_3
ODR_3
STR_3
IDR_4
ODR_4
STR_4
HICR2
Internal data bus
Bus
interface
Legend
IDR_1: Input data register_1
IDR_2: Input data register_2
ODR_1: Output data register_1
ODR_2: Output data register_2
STR_1: Status register_1
STR_2: Status register_2
HICR: Host interface control register
IDR_3: Input data register_3
IDR_4: Input data register_4
ODR_3: Output data register_3
ODR_4: Output data register_4
STR_3: Status register_3
STR_4: Status register_4
HICR2: Host interface control register 2
Figure 18.1 Block Diagram of XBS
Rev. 2.0, 08/02, page 484 of 788