HD64F2145 Datasheet, PDF (397/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

15.4 Operation in Asynchronous Mode
Figure 15.2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by transmit/receive data, a parity bit, and finally stop bits (high
level). In asynchronous serial communication, the transmission line is usually held in the mark
state (high level). The SCI monitors the transmission line, and when it goes to the space state (low
level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and
receiver are independent units, enabling full-duplex communication. Both the transmitter and the
receiver also have a double-buffered structure, so that data can be read or written during
transmission or reception, enabling continuous data transfer and reception.
Idle state
(mark state)
1
LSB
MSB
1
Serial
data
0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
Start
bit
Transmit/receive data
Parity Stop bit
bit
1 bit
7 or 8 bits
1 bit or 1 or 2 bits
none
One unit of transfer data (character or frame)
Figure 15.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits)
15.4.1 Data Transfer Format
Table 15.8 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected according to the SMR setting. For details on the multiprocessor
bit, refer to section 15.5, Multiprocessor Communication Function.
Rev. 2.0, 08/02, page 357 of 788