HD64F2145 Datasheet, PDF (559/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

19.3.5 Output Data Registers 1 to 3 (ODR1 to ODR3)
The ODR registers are 8-bit readable/writable registers for the slave processor (this LSI), and 8-bit
read-only registers for the host processor. The registers selected from the host according to the I/O
address are shown in the following table. For information on ODR3 selection, see section 19.3.3,
LPC Channel 3 Address Register (LADR3). In an LPC I/O read cycle, the data in the selected
register is transferred to the host. The initial values of ODR1 to ODR3 are undefined.
Bits 15 to 4
0000 0000 0110
0000 0000 0110
I/O Address
Bit 3 Bit 2
0
0
0
0
Bit 1
0
1
Bit 0
0
0
Transfer
Cycle
I/O read
I/O read
Host Register Selection
ODR1 read
ODR2 read
19.3.6 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)
The TWR registers are sixteen 8-bit readable/writable registers to both the slave processor (this
LSI) and the host processor. In TWR0, however, two registers (TWR0MW and TWR0SW) are
allocated to the same address for both the host address and the slave address. TWR0MW is a
write-only register for the host processor, and a read-only register for the slave processor, while
TWR0SW is a write-only register for the slave processor and a read-only register for the host
processor. When the host and slave processors begin a write, after the respective TWR0 registers
have been written to, access right arbitration for simultaneous access is performed by checking the
status flags to see if those writes were valid. For the registers selected from the host according to
the I/O address, see section 19.3.3, LPC Channel 3 Address Register (LADR3).
Data transferred in an LPC I/O write cycle is written to the selected register; in an LPC I/O read
cycle, the data in the selected register is transferred to the host. The initial values of TWR0 to
TWR15 are undefined.
Rev. 2.0, 08/02, page 519 of 788