HD64F2145 Datasheet, PDF (26/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Figure 5.5 State Transition in Interrupt Control Mode 1.............................................................101
Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1 ...103
Figure 5.7 Interrupt Exception Handling ....................................................................................104
Figure 5.8 DTC and Interrupt Controller ....................................................................................106
Figure 5.9 Address Break Block Diagram ..................................................................................108
Figure 5.10 Address Break Timing Example..............................................................................110
Figure 5.11 Conflict between Interrupt Generation and Disabling .............................................111
Section 6 Bus Controller
Figure 6.1 Block Diagram of Bus Controller ..............................................................................113
Figure 6.2 ,26 Signal Output Timing.........................................................................................119
Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space)..............................120
Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space) ............................121
Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space..............................................................122
Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space..............................................................123
Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access) ...........................124
Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access) ............................125
Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access)...................................126
Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access) .........................127
Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access) ..........................128
Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access).................................129
Figure 6.13 Example of Wait State Insertion Timing (Pin Wait Mode) .....................................131
Figure 6.14 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1) ....................132
Figure 6.15 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0) ....................132
Figure 6.16 Examples of Idle Cycle Operation...........................................................................133
Section 7 Data Transfer Controller (DTC)
Figure 7.1 Block Diagram of DTC..............................................................................................136
Figure 7.2 Block Diagram of DTC Activation Source Control...................................................141
Figure 7.3 DTC Register Information Location in Address Space .............................................142
Figure 7.4 DTC Operation Flowchart .........................................................................................144
Figure 7.5 Memory Mapping in Normal Mode...........................................................................145
Figure 7.6 Memory Mapping in Repeat Mode............................................................................146
Figure 7.7 Memory Mapping in Block Transfer Mode...............................................................147
Figure 7.8 Chain Transfer Operation ..........................................................................................148
Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)......................149
Figure 7.10 DTC Operation Timing
(Example of Block Transfer Mode, with Block Size of 2).....................................149
Figure 7.11 DTC Operation Timing (Example of Chain Transfer).............................................149
Section 9 8-Bit PWM Timer (PWM)
Figure 9.1 Block Diagram of PWM Timer .................................................................................218
Figure 9.2 Example of Additional Pulse Timing (when Upper 4 Bits of PWDR = 1000) ..........226
Rev. 2.0, 08/02, page xxiv of xxxviii