HD64F2145 Datasheet, PDF (86/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 2.5 Logic Operations Instructions
Instruction Size*
Function
AND
B/W/L
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR
B/W/L
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR
B/W/L
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT
B/W/L
∼ Rd → Rd
Takes the one's complement (logical complement) of data in a general
register.
Note:* Size refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.6 Shift Instructions
Instruction Size*
Function
SHAL
B/W/L
Rd (shift) → Rd
SHAR
Performs an arithmetic shift on data in a general register. 1-bit or 2 bit
shift is possible.
SHLL
B/W/L
Rd (shift) → Rd
SHLR
Performs a logical shift on data in a general register. 1-bit or 2 bit shift is
possible.
ROTL
B/W/L
Rd (rotate) → Rd
ROTR
Rotates data in a general register. 1-bit or 2 bit rotation is possible.
ROTXL
B/W/L
Rd (rotate) → Rd
ROTXR
Rotates data including the carry flag in a general register. 1-bit or 2 bit
rotation is possible.
Note:* Size refers to the operand size.
B: Byte
W: Word
L: Longword
Rev. 2.0, 08/02, page 46 of 788