HD64F2145 Datasheet, PDF (12/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

6.7 Idle Cycle ..........................................................................................................................133
6.8 Bus Arbitration..................................................................................................................134
6.8.1 Priority of Bus Masters ........................................................................................134
6.8.2 Bus Transfer Timing ............................................................................................134
Section 7 Data Transfer Controller (DTC)........................................................ 135
7.1 Features .............................................................................................................................135
7.2 Register Descriptions ........................................................................................................136
7.2.1 DTC Mode Register A (MRA).............................................................................137
7.2.2 DTC Mode Register B (MRB) .............................................................................138
7.2.3 DTC Source Address Register (SAR) ..................................................................138
7.2.4 DTC Destination Address Register (DAR) ..........................................................138
7.2.5 DTC Transfer Count Register A (CRA)...............................................................138
7.2.6 DTC Transfer Count Register B (CRB) ...............................................................139
7.2.7 DTC Enable Registers (DTCER) .........................................................................139
7.2.8 DTC Vector Register (DTVECR) ........................................................................140
7.3 Activation Sources ............................................................................................................140
7.4 Location of Register Information and DTC Vector Table.................................................141
7.5 Operation...........................................................................................................................144
7.5.1 Normal Mode .......................................................................................................145
7.5.2 Repeat Mode ........................................................................................................145
7.5.3 Block Transfer Mode ...........................................................................................146
7.5.4 Chain Transfer......................................................................................................147
7.5.5 Interrupts ..............................................................................................................148
7.5.6 Operation Timing .................................................................................................149
7.5.7 Number of DTC Execution States........................................................................150
7.6 Procedures for Using DTC ................................................................................................151
7.6.1 Activation by Interrupt .........................................................................................151
7.6.2 Activation by Software ........................................................................................151
7.7 Examples of Use of DTC ..................................................................................................152
7.7.1 Normal Mode .......................................................................................................152
7.7.2 Software Activation .............................................................................................153
7.8 Usage Notes.......................................................................................................................154
7.8.1 Module Stop Mode Setting ..................................................................................154
7.8.2 On-Chip RAM......................................................................................................154
7.8.3 DTCE Bit Setting .................................................................................................154
7.8.4 Setting Required on Entering Subactive Mode or Watch Mode ..........................154
7.8.5 DTC Activation by Interrupt Sources of SCI, IIC, LPC, or A/D Converter ........154
Section 8 I/O Ports ............................................................................................ 155
8.1 Overview ...........................................................................................................................155
8.2 Port 1 .................................................................................................................................160
8.2.1 Port 1 Data Direction Register (P1DDR) .............................................................160
Rev. 2.0, 08/02, page x of xxxviii