HD64F2145 Datasheet, PDF (326/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

12.5.6 Timing of Overflow Flag (OVF) Setting
The OVF bit in TCSR is set to 1 when the TCNT overflows (changes from H'FF to H'00). Figure
12.10 shows the timing of OVF flag setting.
Ø
TCNT
Overflow signal
H'FF
H'00
OVF
Figure 12.10 Timing of OVF Flag Setting
12.6 Operation with Cascaded Connection
If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, a single 16-bit timer can be used (16-bit count
mode) or the compare-matches of the 8-bit timer of channel 0 can be counted by the 8-bit timer of
channel 1 (compare-match count mode).
12.6.1 16-Bit Count Mode
When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer
with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
Setting of Compare-Match Flags:
• The CMF flag in TCSR_0 is set to 1 when a 16-bit compare-match occurs.
• The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare-match occurs.
Counter Clear Specification:
• If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare-match, the
16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit compare-match
occurs. The 16-bit counter (TCNT_0 and TCNT_1 together) is also cleared when counter clear
by the TMI0 pin has been set.
• The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be
cleared independently.
Rev. 2.0, 08/02, page 286 of 788