HD64F2145 Datasheet, PDF (452/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 16.5 Flags and Transfer States (Slave Mode)
MST TRS BBSY ESTP STOP IRTR AASX AL
0
0
0
0
0
0
0
0
0
0
1↑
0
0
0
0↓
0
0
1↑/0 1
0
0
0
0
—
*¹
0
0
1
0
0
0
0
—
0
1↑/0 1
0
0
1↑
1↑
—
*¹
0
1
1
0
0
—
—
—
0
1
1
0
0
1↑/0 —
—
*¹
0
1
1
0
0
—
—
0↓
0
1
1
0
0
—
—
—
0
1
1
0
0
—
—
0↓
0
1
1
0
0
1↑/0 —
0
*²
0
0
1
0
0
1↑/0 —
—
*²
0
0
1
0
0
—
—
0↓
AAS
0
0
1↑
1↑
0
—
—
0↓
—
0↓
0
—
0↓
ADZ
0
0
0
1↑
0
0
0
0
1
0
0
—
0↓
ACKB
0
0
0
0
0
1↑
0
0
0
0
0
—
—
ICDRF
—
—
1↑
1↑
1↑
—
—
—
1↑
0↓
ICDRE
0
1↑
1
1
1
—
1↑
0↓
1
0↓
1↑
—
—
State
Idle state (flag
clearing
required)
Start condition
detected
SAR match in
first frame
(SARX≠SAR)
General call
address match
in first frame
(SARX≠H’00)
SARS match
in first frame
(SAR≠SARX)
Transmission
end (ACKE=1
and ACKB=1)
Transmission
end with
ICDRE=0
ICDR write
with the above
state
Transmission
end with
ICDRE=1
ICDR write
with the above
state
Automatic
data transfer
from ICDRT to
ICDRS with
the above
state
Reception end
with ICDRF=0
ICDR read
with the above
state
Rev. 2.0, 08/02, page 412 of 788