HD64F2145 Datasheet, PDF (518/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

17.4.6 KBF Setting Timing and KCLK Control
Figure 17.11 shows the KBF setting timing and the KCLK pin states.
ø*
KCLK
(pin)
Internal
KCLK
Falling edge
signal
RXCR3 to
RXCR0
B'1010
KBF
KCLK
(output)
11th fall
B'0000
Automatic I/O inhibit
Note:* The ø clock shown here is scaled by 1/N in medium-speed mode when the operating
mode is active mode.
Figure 17.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing
Rev. 2.0, 08/02, page 478 of 788