HD64F2145 Datasheet, PDF (139/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

5.6 Interrupt Control Modes and Interrupt Operation
The interrupt controller has two modes: Interrupt control mode 0 and interrupt control mode 1.
Interrupt operations differ depending on the interrupt control mode. NMI interrupts and address
break interrupts are always accepted except for in reset state or in hardware standby mode. The
interrupt control mode is selected by SYSCR. Table 5.4 shows the interrupt control modes.
Table 5.4 Interrupt Control Modes
Interrupt
SYSCR
Control
Mode INTM1 INTM0
0
0
0
1
1
Priority
Setting
Registers
ICR
ICR
Interrupt
Mask Bits
I
I, UI
Description
Interrupt mask control is performed by
the I bit. Priority levels can be set with
ICR.
3-level interrupt mask control is
performed by the I bit. Priority levels
can be set with ICR.
5.6.1 Interrupt Control Mode 0
In interrupt control mode 0, interrupt requests other than NMI and address breaks are masked by
ICR and the I bit of the CCR in the CPU. Figure 5.4 shows a flowchart of the interrupt acceptance
operation.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. According to the interrupt control level specified in ICR, the interrupt controller only accepts
an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt
request with interrupt control level 0 (no priority). If several interrupt requests are issued, an
interrupt request with the highest priority is accepted according to the priority order, an
interrupt handling is requested to the CPU, and other interrupt requests are held pending.
3. If the I bit in CCR is set to 1, only NMI and address break interrupts are accepted by the
interrupt controller, and other interrupt requests are held pending. If the I bit is cleared to 0,
any interrupt request is accepted.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
6. Next, the I bit in CCR is set to 1. This masks all interrupts except for NMI and address break
interrupts.
Rev. 2.0, 08/02, page 99 of 788