HD64F2145 Datasheet, PDF (510/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit Bit Name Initial Value R/W
3 RXCR3 0
R
2 RXCR2 0
R
1 RXCR1 0
R
0 RXCR0 0
R
Description
Receive Counter
These bits indicate the received data bit. Their value is
incremented on the fall of KCLK. These bits cannot be
modified.
The receive counter is initialized to 0000 by a reset
and when 0 is written in KBE. Its value returns to 0000
after a stop bit is received.
0000: —
0001: Start bit
0010: KB0
0011: KB1
0100: KB2
0101: KB3
0110: KB4
0111: KB5
1000: KB6
1001: KB7
1010: Parity bit
1011: —
11- - : —
17.3.3 Keyboard Data Buffer Register (KBBR)
KBBR stores receive data. Its value is valid only when KBF = 1.
Bit Bit Name Initial Value R/W
7 KB7
0
R
6 KB6
0
R
5 KB5
0
R
4 KB4
0
R
3 KB3
0
R
2 KB2
0
R
1 KB1
0
R
0 KB0
0
R
Description
Keyboard Data 7 to 0
8-bit read only data.
Initialized to H'00 by a reset, in standby mode, watch
mode, subactive mode, subsleep mode, and module
stop mode, and when KBIOE is cleared to 0.
Rev. 2.0, 08/02, page 470 of 788