HD64F2145 Datasheet, PDF (544/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Figure 19.1 shows a block diagram of the LPC.
TWR0MW
TWR1–15
IDR3
IDR2
IDR1
Cycle detection
Module data bus
Parallel → serial conversion
SIRQCR0
SIRQCR1
SERIRQ
Serial → parallel conversion
Control logic
HISEL
Address match
LAD0–
LAD3
H'0060/64
H'0062/66
LADR3
LSCIE
LSCIB
LSCI input
LSMIE
LSMIB
LSMI input
PB1 I/O
LCLK
LSCI
Serial ← parallel conversion
PMEE
PMEB
PME input
PB0 I/O
SYNC output
HICR0
P80 I/O
TWR0SW
TWR1–15
ODR3
ODR2
ODR1
HICR1
HICR2
HICR3
GA20
STR3
STR2
STR1
Internal interrupt
control
IBFI1
IBFI2
IBFI3
ERRI
Legend
HICR0 to HICR3: Host interface control registers 0 to 3
LADR3H, 3L: LPC channel 3 address register 3H and 3L
IDR1 to IDR3: Input data registers 1 to 3
ODR1 to DOR3: Output data registers 1 to 3
STR1 to STR3: Status registers 1 to 3
TWR0MW: Two-way register 0MW
TWR0SW: Two-way register 0SW
TWR1 to TWR15: Two-way data registers 1 to 15
SERIRQ0, 1: SERIEQ control registers 0 and 1
HISEL: Host interface select register
Figure 19.1 Block Diagram of LPC
Rev. 2.0, 08/02, page 504 of 788