HD64F2145 Datasheet, PDF (109/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

3.3 Operating Mode Descriptions
3.3.1 Mode 1
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled.
Ports 1 and 2 function as an address bus, port 3 functions as a data bus, and part of port 9 carries
bus control signals. Clearing the ABW bit to 0 in the WSCR register makes port B a data bus.
3.3.2 Mode 2
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
After a reset, the LSI is set to single-chip mode. To access an external address space, bit EXPE in
MDCR should be set to 1.
When the EXPE bit in MDCR is set to 1, ports 1, 2 and A function as input ports after a reset.
Ports 1, 2 and A output an address by setting 1 to the corresponding port data direction register
(DDR). Port 3 functions as a data bus, and parts of port 9 carry bus control signals. Port B
functions as a data bus when the ABW bit in WSCR is cleared to 0.
3.3.3 Mode 3
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled. The
CPU can access a 56-kbyte address space in mode 3.
After a reset, the LSI is set to single-chip mode. To access an external address space, bit EXPE in
MDCR should be set to 1.
When the EXPE bit in MDCR is set to 1, ports 1 and 2 function as input ports after a reset. Ports 1
and 2 function as an address bus by setting 1 to the corresponding port data direction register
(DDR). Port 3 functions as a data bus, and parts of port 9 carry bus control signals. Port B
functions as a data bus when the ABW bit in WSCR is cleared to 0.
3.3.4 Pin Functions in Each Operating Mode
Pin functions of ports 1 to 3, 9, A, and B depend on the operating mode. Table 3.2 shows pin
functions in each operating mode.
Rev. 2.0, 08/02, page 69 of 788