HD64F2145 Datasheet, PDF (805/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Item
Page Revisions (See Manual for Details)
8.16.4 Port G Nch-OD
Control Register
(PGNOCR)
216 Bit description amended.
1: Vss-side N-channel open drain
Section 9 8-Bit PWM
Timer (PWM)
9.3.2 PWM Data
Registers (PWDR0 to
PWDR15)
222 Description added.
PWDR0 to PWDR15 are initialized to H'00.
9.5 Usage Note
226 Added.
9.5.1 Module Stop Mode
Setting
Section 10 14-Bit PWM 228 Description added.
Timer (PWMX)
Since DACNT consists of 16-bit data, DACNT transfers data
10.3.1 PWM (D/A)
to the CPU via the temporary register (TEMP).
Counters H and L
(DACNTH, DACNTL)
10.3.2 PWM (D/A) Data 230 Description added.
Registers A and B
(DADRA, DADRB)
Since DADR consists of 16-bit data, DADR transfers data to
the CPU via the temporary register (TEMP).
10.5 Operation
237 Description of additional pulse added.
to 239
10.6 Usage Note
240 Added.
10.6.1 Module Stop Mode
Setting
Section 11 16-Bit Free- 242 Legend
Running Timer (FRT)
OCRDM: Output compare register DM (16-bit)
11.1 Features
Figure 11.1 Block
Diagram of 16-Bit Free-
Running Timer
11.3.7 Timer
249 Description of bit 1 amended.
Control/Status Register
(TCSR)
(Error) Overflow Flag
(Correction) Timer Overflow
Rev. 2.0, 08/02, page 765 of 788