HD64F2145 Datasheet, PDF (325/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

12.5.4 Timing of Counter Clear at Compare-Match
TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of
the CCLR1 and CCLR0 bits in TCR. Figure 12.8 shows the timing of clearing the counter by a
compare-match.
Ø
Compare-match
signal
TCNT
N
H'00
Figure 12.8 Timing of Counter Clear by Compare-Match
12.5.5 TCNT External Reset Timing
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure
12.9 shows the timing of clearing the counter by an external reset input.
Ø
External reset
input pin
Clear signal
TCNT
N–1
N
H'00
Figure 12.9 Timing of Counter Clear by External Reset Input
Rev. 2.0, 08/02, page 285 of 788