HD64F2145 Datasheet, PDF (529/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit
Bit Name
Initial
Value
R/W
Slave Host
Description
0
FGA20E 0
R/W 
Fast A20 Gate Function Enable
When P81DDR=0:
0: XBS fast A20 gate function disabled
1: Setting prohibited
When P81DDR=1:
0: XBS fast A20 gate function disabled
1: XBS fast A20 gate function enabled
When the fast A20 gate is disabled, the normal
A20 gate can be implemented by the firmware
operation of the P81 output.
When the host interface (XBS) fast A20 gate
function is enabled, the DDR bit for P81 must
be set to 1. Therefore, the state of the
P81/GA20 pin cannot be monitored by reading
the DR bit for P81.
A fast A20 gate function is also provided in the
LPC. The state of the P81/GA20 pin can be
monitored by reading the LPC’s GA20 bit.
Rev. 2.0, 08/02, page 489 of 788