HD64F2145 Datasheet, PDF (521/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

17.5 Usage Notes
17.5.1 KBIOE Setting and KCLK Falling Edge Detection
When KBIOE is 0, the internal KCLK and internal KD settings are fixed at 1. Therefore, if the
KCLK pin is low when the KBIOE bit is set to 1, the edge detection circuit operates and the
KCLK falling edge is detected.
If the KBFSEL bit and KBE bit are both 0 at this time, the KBF bit is set. Figure 17.14 shows the
timing of KBIOE setting and KCLK falling edge detection.
T1
T2
ø
KCLK (pin)
Internal KCLK
(KCLKI)
KBIOE
Falling edge
signal
KBFSEL
KBE
KBF
Figure 17.14 KBIOE Setting and KCLK Falling Edge Detection Timing
17.5.2 Module Stop Mode Setting
Keyboard buffer controller operation can be enabled or disabled using the module stop control
register. The initial setting is for keyboard buffer controller operation to be halted. Register access
is enabled by canceling module stop mode. For details, refer to section 26, Power-Down Modes.
Rev. 2.0, 08/02, page 481 of 788