HD64F2145 Datasheet, PDF (155/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

6.3.1 Bus Control Register (BCR)
BCR is used to specify the access mode for the external address space or the I/O area range when
the $6/,26 pin is specified as an I/O strobe pin.
Bit Bit Name Initial Value R/W
7
—
1
R/W
6
ICIS0
1
R/W
5
BRSTRM 0
R/W
4
BRSTS1 1
R/W
3
BRSTS0 0
R/W
2

0
R/W
1
IOS1
1
R/W
0
IOS0
1
R/W
Description
Reserved
This bit should not be written by 0.
Idle Cycle Insertion
Selects whether or not to insert 1-state of the idle
cycle between bus cycles when the external
write cycle follows the external read cycle.
0: Idle cycle not inserted when the external write
cycle follows the external read cycle
1: 1-state idle cycle inserted when the external
write cycle follows the external read cycle
Burst ROM Enable
Selects the bus interface for the external address
space.
0: Basic bus interface
1: Burst ROM interface
Burst Cycle Select 1
Selects the number of states in the burst cycle of
the burst ROM interface.
0: 1 state
1: 2 states
Burst Cycle Select 0
Selects the number of words that can be
accessed by burst access via the burst ROM
interface.
0: Max, 4 words
1: Max, 8 words
Reserved
This bit should not be written by 0.
IOS Select 1, 0
Select the address range where the ,26 signal is
output. For details, refer to table 6.3.
Rev. 2.0, 08/02, page 115 of 788