HD64F2145 Datasheet, PDF (562/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

• STR2
R/W
Bit Bit Name Initial Value Slave Host Description
7 DBU27 0
R/W R Defined by User
6 DBU26 0
R/W R The user can use these bits as necessary.
5 DBU25 0
R/W R
4 DBU24 0
R/W R
3 C/'2
0
R
R Command/Data
When the host processor writes to an IDR register, bit
2 of the I/O address is written into this bit to indicate
whether IDR contains data or a command.
0: Contents of data register (IDR) are data
1: Contents of data register (IDR) are a command
2 DBU22 0
R/W R Defined by User
The user can use this bit as necessary.
1 IBF2
0
R
R Input Buffer Full
Set to 1 when the host processor writes to IDR. This
bit is an internal interrupt source to the slave
processor (this LSI). IBF is cleared to 0 when the
slave processor reads IDR.
The IBF1 flag setting and clearing conditions are
different when the fast A20 gate is used. For details
see table 19.3.
0: [Clearing condition]
When the slave processor reads IDR
1: [Setting condition]
When the host processor writes to IDR using I/O write
cycle
0 OBF2 0
R/(W)* R Output Buffer Full
Set to 1 when the slave processor (this LSI) writes to
ODR. Cleared to 0 when the host processor reads
ODR.
0: [Clearing condition]
When the host processor reads ODR using I/O read
cycle, or the slave processor writes 0 to the OBF bit
1: [Setting condition]
When the slave processor writes to ODR
Note:* Only 0 can be written to clear the flag.
Rev. 2.0, 08/02, page 522 of 788