HD64F2145 Datasheet, PDF (558/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Table 19.2 Register Selection
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
%LW#7
%LW#7
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
0
0
I/O Address
Bit 2 Bit 1
0
Bit 1
1
Bit 1
0
Bit 1
1
Bit 1
0
0
0
0
Bit 0
0
0
0
0
0
1
Transfer
Cycle
I/O write
I/O write
I/O read
I/O read
I/O write
I/O write
Host Register Selection
IDR3 write, C/'3 ← 0
IDR3 write, C/'3 ← 1
ODR3 read
STR3 read
TWR0MW write
TWR1 to TWR15 write
1
1
1
1
%LW#7 0
0
0
0
I/O read TWR0SW read
%LW#7 0
0
0
1
I/O read TWR1 to TWR15 read
1
1
1
1
19.3.4 Input Data Registers 1 to 3 (IDR1 to IDR3)
The IDR registers are 8-bit read-only registers for the slave processor (this LSI), and 8-bit write-
only registers for the host processor. The registers selected from the host according to the I/O
address are shown in the following table. For information on IDR3 selection, see section 19.3.3,
LPC Channel 3 Address Register (LADR3). Data transferred in an LPC I/O write cycle is written
to the selected register. The state of bit 2 of the I/O address is latched into the C/' bit in STR, to
indicate whether the written information is a command or data. The initial values of IDR1 to IDR3
are undefined.
Bits 15 to 4
0000 0000 0110
0000 0000 0110
0000 0000 0110
0000 0000 0110
I/O Address
Bit 3 Bit 2
0
0
0
1
0
0
0
1
Bit 1
0
0
1
1
Bit 0
0
0
0
0
Transfer
Cycle
I/O write
I/O write
I/O write
I/O write
Host Register Selection
IDR1 write, C/'1 ← 0
IDR1 write, C/'1 ← 1
IDR2 write, C/'2 ← 0
IDR2 write, C/'2 ← 1
Rev. 2.0, 08/02, page 518 of 788