HD64F2145 Datasheet, PDF (385/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

15.3.6 Serial Control Register (SCR)
SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt
requests, and selection of the transfer clock source. For details on interrupt requests, refer to
section 15.8, Interrupt Sources.
Bit
Bit Name Initial Value R/W Description
7
TIE
0
R/W Transmit Interrupt Enable
When this bit is set to 1, a TXI interrupt request is
enabled.
6
RIE
0
R/W Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
5
TE
0
R/W Transmit Enable
When this bit is set to 1, transmission is enabled.
4
RE
0
R/W Receive Enable
When this bit is set to 1, reception is enabled.
3
MPIE
0
R/W Multiprocessor Interrupt Enable (enabled only when
the MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and ORER status flags in SSR is
disabled. On receiving data in which the
multiprocessor bit is 1, this bit is automatically
cleared and normal reception is resumed. For
details, refer to section 15.5, Multiprocessor
Communication Function.
2
TEIE
0
R/W Transmit End Interrupt Enable
When this bit is set to 1, a TEI interrupt request is
enabled.
Rev. 2.0, 08/02, page 345 of 788