HD64F2145 Datasheet, PDF (388/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Bit
Bit Name Initial Value R/W
4
FER
0
R/(W)*
3
PER
0
R/(W)*
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
Note:* Only 0 can be written, to clear the flag.
Description
Framing Error
[Setting condition]
• When the stop bit is 0
[Clearing condition]
• When 0 is written to FER after reading FER =
1
In 2-stop-bit mode, only the first stop bit is
checked.
Parity Error
[Setting condition]
• When a parity error is detected during
reception
[Clearing condition]
• When 0 is written to PER after reading PER =
1
Transmit End
[Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit
of a 1-byte serial transmit character
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE
=1
• When a TXI interrupt request is issued
allowing the DTC to write data to TDR
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive
frame. When the RE bit in SCR is cleared to 0 its
previous state is retained.
Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to
the transmit frame.
Rev. 2.0, 08/02, page 348 of 788