HD64F2145 Datasheet, PDF (314/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

TCR
STCR
Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description
TMR_1 0
0
0
—
—
Disables clock input
0
0
1
0
—
Increments at falling edge of internal clock
ø/8
0
0
1
1
—
Increments at falling edge of internal clock
ø/2
0
1
0
0
—
Increments at falling edge of internal clock
ø/64
0
1
0
1
—
Increments at falling edge of internal clock
ø/128
0
1
1
0
—
Increments at falling edge of internal clock
ø/1024
0
1
1
1
—
Increments at falling edge of internal clock
ø/2048
1
0
0
—
—
Increments at compare-match A from
TCNT_0*
TMR_Y 0
0
0
—
—
Disables clock input
0
0
1
—
—
Increments at falling edge of internal clock
ø/4
0
1
0
—
—
Increments at falling edge of internal clock
ø/256
0
1
1
—
—
Increments at falling edge of internal clock
ø/2048
1
0
0
—
—
Disables clock input
TMR_X 0
0
0
—
—
Disables clock input
0
0
1
—
—
Increments at falling edge of internal clock
ø
0
1
0
—
—
Increments at falling edge of internal clock
ø/2
0
1
1
—
—
Increments at falling edge of internal clock
ø/4
1
0
0
—
—
Disables clock input
Common 1
0
1
—
—
Increments at rising edge of external
clock
1
1
0
—
—
Increments at falling edge of external
clock
1
1
1
—
—
Increments at both rising and falling
edges of external clock.
Note:* If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock input is
set as the TCNT_0 compare-match signal simultaneously, a count-up clock cannot be
generated.
Rev. 2.0, 08/02, page 274 of 788