HD64F2145 Datasheet, PDF (807/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Item
Section 12 8-Bit Timer
(TMR)
12.1 Features
Figure 12.2 Block
Diagram of 8-Bit Timers
(TMR_Y and TMR_X)
Page
267
268
269
Revisions (See Manual for Details)
(Error)
• Timer output controlled by two compare-match signals
 The timer output signal in each channel is controlled by
two independent compare-match signals, enabling the
timer to be used for various applications, such as the
generation of pulse output or PWM output with an
arbitrary duty cycle.
(Correction)
• Timer output controlled by two compare-match signals
 The timer output signal in each channel is controlled by
two independent compare-match signals, enabling the
timer to be used for various applications, such as the
generation of pulse output or PWM output with an
arbitrary duty cycle. (The TMR_Y does not have a
timer output pin.)
(Error)
• Cascading of two channels
 Cascading of TMR_0 and TMR_1
(Correction)
• Cascading of TMR_0 and TMR_1
 (TMR_Y and TMR_X cannot be cascaded.)
(Error)
Figure 12.1 Block Diagram of 8-Bit Timers (TMR_0, TMR_1,
TMR_X, and TMR_Y)
(Correction)
Figure 12.1 Block Diagram of 8-Bit Timers (TMR_0 and
TMR_1)
Added.
Rev. 2.0, 08/02, page 767 of 788