HD64F2145 Datasheet, PDF (137/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

An interrupt control level can be specified for a module to which an ICR bit is assigned. Interrupt
requests from modules that are set to control level 1 (priority) by the ICR bit setting and the I and
UI bits in CCR are given priority and processed before interrupt requests from modules that are set
to control level 0 (no priority).
Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities
Origin of
Interrupt
Source
Name
External pin NMI
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6, KIN7 to KIN0
IRQ7, KIN15 to KIN8, WUE7 to
WUE0
DTC
SWDTEND (Software activation
data transfer end)
WDT_0
WOVI0 (Interval timer)
WDT_1
WOVI1 (Interval timer)
—
Address break
A/D
converter
ADI (A/D conversion end)
—
Reserved for system use
FRT
ICIA (Input capture A)
ICIB (Input capture B)
ICIC (Input capture C)
ICID (Input capture D)
OCIA (Output compare A)
OCIB (Output compare B)
FOVI (Overflow)
Reserved for system use
—
Reserved for system use
TMR_0
CMIA0 (Compare match A)
CMIB0 (Compare match A)
OVI0 (Overflow)
Reserved for system use
Vector Address
Vector Normal
Number Mode
Advanced
Mode
7
H'000E
H'00001C
16
H'0020
H'000040
17
H'0022
H'000044
18
H'0024
H'000048
19
H'0026
H'00004C
20
H'0028
H'000050
21
H'002A
H'000054
22
H'002C
H'000058
23
H'002E
H'00005C
ICR
—
ICRA7
ICRA6
ICRA5
Priority
High
ICRA4
ICRA3
24
H'0030
H'000060
ICRA2
25
H'0032
H'000064
ICRA1
26
H'0034
H'000068
ICRA0
27
H'0036
H'00006C
—
28
H'0038
H'000070
ICRB7
29
H’003A
H’000074
—
to
to
to
47
H’005E
H’0000BC
48
H'0060
H'0000C0
ICRB6
49
H'0062
H'0000C4
50
H'0064
H'0000C8
51
H'0066
H'0000CC
52
H'0068
H'0000D0
53
H'006A
H'0000D4
54
H'006C
H'0000D8
55
H'006E
H'0000DC
56
H’0070
H’0000E0
—
to
to
to
63
H’007E
H’0000FC
64
H'0080
H'000100
ICRB3
65
H'0082
H'000104
66
H'0084
H'000108
67
H'0086
H'00010C
Low
Rev. 2.0, 08/02, page 97 of 788