HD64F2145 Datasheet, PDF (548/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

R/W
Bit Bit Name Initial Value Slave Host Description
4 FGA20E 0
R/W — Fast A20 Gate Function Enable
Enables or disables the fast A20 gate function. When
the fast A20 gate is disabled, the normal A20 gate
can be implemented by firmware operation of the
P81 output.
When the fast A20 gate function is enabled, the DDR
bit for P81 must not be set to 1.
0: Fast A20 gate function disabled
• Other function of pin P81 is enabled
• GA20 output internal state is initialized to 1
1: Fast A20 gate function enabled
• GA20 pin output is open-drain (external VCC pull-
up resistor required)
3 SDWNE 0
R/W — LPC Software Shutdown Enable
Controls host interface shutdown. For details of the
LPC shutdown function, and the scope of initialization
by an LPC reset and an LPC shutdown, see section
19.4.4, Host Interface Shutdown Function (LPCPD).
0: Normal state, LPC software shutdown setting
enabled
[Clearing conditions]
• Writing 0
• LPC hardware reset or LPC software reset
• LPC hardware shutdown release (rising edge of
/3&3' signal)
1: LPC hardware shutdown state setting enabled
• Hardware shutdown state when /3&3' signal is
low
[Setting condition]
• Writing 1 after reading SDWNE = 0
Rev. 2.0, 08/02, page 508 of 788