HD64F2145 Datasheet, PDF (390/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

15.3.9 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 15.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and
clocked synchronous mode. The initial value of BRR is H'FF, and it can be read from or written to
by the CPU at all times.
Table 15.2 Relationships between N Setting in BRR and Bit Rate B
Mode
Asynchronous mode
Bit Rate
Ø × 10⁶
B=
64 × 2 ^2n-1 × (N+1)
Error
Ø × 10⁶
Error (%) = {
- 1 } × 100
B × 64 × 2 ^2n-1 × (N+1)
Clocked synchronous mode
Ø × 10⁶
—
B=
64 × 2 ^2n-1 × (N+1)
Legend
B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
ø: Operating frequency (MHz)
n: Determined by the SMR settings shown in the following table.
SMR Setting
CKS1
CKS0
n
0
0
0
0
1
1
1
0
2
1
1
3
Table 15.3 shows sample N settings in BRR in normal asynchronous mode. Table 15.4 shows the
maximum bit rate settable for each frequency. Table 15.6 shows sample N settings in BRR in
clocked synchronous mode. Tables 15.5 and 15.7 show the maximum bit rates with external clock
input.
Rev. 2.0, 08/02, page 350 of 788