HD64F2145 Datasheet, PDF (439/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

16.3.3 Second Slave Address Register (SARX)
SARX sets the second slave address and selects the communication format. In slave mode,
transmit/receive operations by the DTC are possible when the received address matches the
second slave address. If the LSI is in slave mode with the I²C bus format selected, when the FSX
bit is set to 0 and the upper 7 bits of SARX match the upper 7 bits of the first frame received after
a start condition, the LSI operates as the slave device specified by the master device. SARX can be
accessed only when the ICE bit in ICCR is cleared to 0.
Bit Bit Name Initial Value R/W
7 SVAX6 0
R/W
6 SVAX5 0
R/W
5 SVAX4 0
R/W
4 SVAX3 0
R/W
3 SVAX2 0
R/W
2 SVAX1 0
R/W
1 SVAX0 0
R/W
0 FSX
1
R/W
Description
Second Slave Address 6 to 0
Set the second slave address.
Format Select X
Selects the communication format together with the FS bit
in SAR and the SW bit in DDCSWR. Refer to table 16.2.
Rev. 2.0, 08/02, page 399 of 788