HD64F2145 Datasheet, PDF (315/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

12.3.5 Timer Control/Status Register (TCSR)
TCSR indicates the status flags and controls compare-match output.
• TCSR_0
Bit Bit Name Initial Value R/W Description
7
CMFB 0
R/(W)* Compare-Match Flag B
[Setting condition]
When the values of TCNT_0 and TCORB_0 match
[Clearing conditions]
• Read CMFB when CMFB = 1, then write 0 in CMFB
• When the DTC is activated by a CMIB interrupt
6
CMFA 0
R/(W)* Compare-Match Flag A
[Setting condition]
When the values of TCNT_0 and TCORA_0 match
[Clearing conditions]
• Read CMFA when CMFA = 1, then write 0 in CMFA
• When the DTC is activated by a CMIA interrupt
5
OVF
0
R/(W)* Timer Overflow Flag
[Setting condition]
When TCNT_0 overflows from H'FF to H'00
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
4
ADTE 0
R/W A/D Trigger Enable
Enables or disables A/D converter start requests by
compare-match A.
0: A/D converter start requests by compare-match A are
disabled
1: A/D converter start requests by compare-match A are
enabled
Rev. 2.0, 08/02, page 275 of 788