HD64F2145 Datasheet, PDF (469/829 Pages) Renesas Technology Corp – Hitachi 16-Bit Single-Chip Microcomputer

Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high,
and generates the stop condition.
Start condition generation
SCL
(master output)
SDA
(master output)
SDA
(slave output)
[5]
ICDRE
1
2
3
4
5
6
7
8
9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Slave address
R/W [7]
A
IRIC
IRTR
Interrupt
request
Interrupt
request
ICDRT
Address + R/
ICDRS
Address + R/
1
2
Bit 7 Bit 6
Data 1
Data 1
Data 1
Note:* Data write
in ICDR
prohibited
User processing
[4] BBSY set to 1
SCP cleared to 0
[6] ICDR write
(start condition issuance)
[6] IRIC clear
[9] ICDR write
[9] IRIC clear
Figure 16.9 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0)
SCL
(master output)
8
9
SDA
(master output)
Bit 0
Data 1
[7]
SDA
A
(slave output)
ICDRE
IRIC
IRTR
ICDR
Data 1
1
2
3
4
5
6
7
8
9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data 2
[10]
A
Start condition issuance
Data 2
User processing [9] ICDR write
[9] IRIC clear
[11] ACKB read
[12] Set BBSY=1and
SCP=0
[12] IRIC clear ^{(Stop condition issuance)}
Figure 16.10 Example of Stop Condition Issuance Operation Timing
in Master Transmit Mode (MLS = WAIT = 0)
Rev. 2.0, 08/02, page 429 of 788